Active Projects

BAR always has a number of ongoing projects. The list below contains the projects that are currently active.


ASPIRE is a new 5-year research project that recognizes the shift from transistor-scaling-driven performance improvements to a new post-scaling world where whole-stack co-design is the key to improved efficiency. Building on the success of the Par Lab project, it uses deep hardware and software co-tuning to achieve the highest possible performance and energy efficiency for future warehouse-scale and mobile computing systems.

Berkeley Out-of-Order Machine

BOOM is Berkeley's out-of-order core generator. Our goal is to provide a readable, open-source implementatino for use in education, research, and industry.


The FireBox project aims to develop a system architecture for third-generation Warehouse-Scale Computers (WSCs). Firebox scales up to a ~1 MegaWatt WSC containing up to 10,000 compute nodes and up to an Exabyte (2^60 Bytes) of non-volatile memory connected via a low-latency, high-bandwidth optical switch. The FireBox project will produce custom datacenter SoCs, distributed simulation tools for warehouse-scale machines, and systems software for FireBox-style disaggregated datacenters.


FireSim provides easy-to-use, scalable, FPGA-accelerated cycle-accurate hardware simulation in the public cloud.


FIRRTL (A Flexible Intermediate Representation for RTL) is motivated by the success of Chisel and has two parts: 1) a specification of the formalized elaborated graph that the Chisel DSL produces, prior to any simplification, and 2) a library of micro-passes that are used to simplify, transform, or specialize arbitrary FIRRTL graphs.


The Berkeley Graph Algorithm Platform (GAP) Project spans the entire stack, and it aims to accelerate graph algorithms through software optimization and hardware acceleration.

Accelerating Genomic Analytics

Accelerating genomic analytics using hardware specialization.


The Hurricane project aims to build the next generation of chips coming out of UC Berkeley. These chips will be focused on power-efficient DSP, with the goal being to beat traditional DSP architectures in energy/op (like TI's TMS320xx67xx series) while maintaining the familiar programming enviornment availiable to traditional CPU-based systems. Specifically this means booting a full Linux environment, maintaining cache coherence over the entire chip, and supporting existing programming models like OpenCL and pthreads.


The Hwacha project is developing a new vector architecture for future computer systems that are constrained in their power and energy consumption.


MIDAS — Modeling Infrastructure for Debugging and Simulation — is a heterogeneous-host platform framework for fast, cycle accurate-simulation of digital systems ranging from single-chip multiprocessors and accelerators to models of warehouse-scale computers such as FireBox.

Silicon Photonics

Today’s computers are largely limited by the amount of information they can communicate at every level of system hierarchy: the processor chip, server blade, rack and data-center. Silicon photonics is an emerging technology with the potential to overcome traditional communication limitations. We are leveraging the high-bandwidth density and low-energy use of photonic interconnects to prototype and build new electronic-photonic chips and systems.


The Raven project integrated circuits and architecture research to realize extreme energy efficiency in processor designs. Leveraging RISC-V and the Rocket Chip, Raven silicon achieved 26.2 GFLOPS/W via a novel switched-capacitor DC-DC converter architecture.

RISC-V Instruction Set Architecture

RISC-V is a new free and open instruction set architecture (ISA) developed at UC Berkeley, initially designed for research and education, but is now increasingly being used for commercial designs. A full set of software tools for the architecture are also under development and are being prepared for open distribution. RISC-V was initially developed as part of Par Lab and is now part of ASPIRE.

Rocket Chip Generator

Rocket Chip is Berkeley's RISC-V based SOC generator. The open-source release is capable of generating a multi-core system with Rocket scalar cores, Z-Scale control processors, and a coherent memory system.

Strober: A Fast and Accurate Sample-Based Energy Simulation Framework for Arbitrary RTL

The Strober project is motivated by the fact that fast and accurate energy evaluation of long-running applications on complex hardware designs is extremely difficult. By taking random RTL state snapshots of FPGA-accelerated simulations, Strober can achieve four-orders-of-magnitude of speedup over commercial CAD tools with less than 5% errors with 99% confidence.


TileLink is a protocol designed to be a substrate for cache coherence transactions implementing a particular cache coherence policy within an on-chip memory hierarchy. Its purpose is to orthogonalize the design of the on-chip network and the implementation of the cache controllers from the design of the coherence protocol itself. Any cache coherence protocol that conforms to TileLink's transaction structure can be used interchangeably with the physical networks and cache controllers we provide as part of the Rocket Chip Genereator.

AWS Marketplace Support

Finding support for projects from Berkeley Architecture Research hosted on AWS Marketplace.