RISC-V Instruction Set Architecture
RISC-V is a new free and open instruction set architecture (ISA) developed at UC Berkeley, initially designed for research and education, but is now increasingly being used for commercial designs. A full set of software tools for the architecture are also under development and are being prepared for open distribution. RISC-V was initially developed as part of Par Lab and is now part of ASPIRE.
RISC-V Hardware Implementations
The BAR github page contains all the projects
that BAR members are working on. Since the RISC-V ISA was developed here and
was designed to aid research, many of the projects on this website are at least
somehow RISC-V related. The most relevant ones are:
- RocketChip: A paramaterizable
RISC-V chip generator
RISC-V Software Stack
Since the RISC-V project has gained significant momentum outside of Berkeley,
many of the components of the RISC-V software stack have been spun off into the
RISC-V github organization. One of the major
reasons for this split was to make it easier for external contributors to have
write access to the relevant repositories.
Some of the most interesting projects hosted at the RISC-V github
- riscv-gnu-toolchain: A port
of the GNU toolchain (binutils, GCC, and glibc) to the RISC-V ISA. This port
is in the process of being upstreamed.
- riscv-poky: A port of OpenEmbedded, an
embedded Linux distribution, to RISC-V.
The RISC-V organization serves to foster the development of the RISC-V ISA.