Rocket Chip Generator

Rocket Chip is Berkeley's RISC-V based SOC generator. The open-source release is capable of generating a multi-core system with Rocket scalar cores, Z-Scale control processors, and a coherent memory system.

Rocket Chip is BAR's paramaterizable chip generator, and serves as the basis for all the RISC-V implementations that we produce. Rocket Chip can generate a RTL RISC-V implementation that has virtual memory, a coherent multi-level cache hierarchy, IEEE-compliant floating-point units, and all the relevant infastructure to talk to a running system.

The best description of how to get started with Rocket Chip is the README.