The Strober project is motivated by the fact that fast and accurate energy evaluation of long-running applications on complex hardware designs is extremely difficult. By taking random RTL state snapshots of FPGA-accelerated simulations, Strober can achieve four-orders-of-magnitude of speedup over commercial CAD tools with less than 5% errors with 99% confidence.
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Sample-based energy simulation accurately and quickly estimates performance and average power by obtaining random RTL state sample snapshots from fast simulations and replaying the sample snapshots on slow but detailed simulations. The central limit theorem states that the sampling error depends only on the sample size and the variance of execution, not on the length of execution. Thus, the longer we simulate the target designs, the more speedup we can achieve through this methodology.
Strober is an implementation of sample-based energy simulation developed in UC Berkeley. Strober is built upon Chisel, taking advantage of hardware generators and custom transforms. Strober automatically generates FPGA performance simulators from arbitrary RTL designs written in Chisel, thus minimizing the designers' manual efforts. Strober also adds scan chains and I/O trace buffers to read out the RTL state sample snapshots from the FGPA simulation.
The random RTL state sample snapshots are replayed on gate-level simulation for the average power estimation. The replay tool flow is built using industry-standard CAD tools, widely available to academic research through academic license programs . Strober provides custom VPI routines to replay the RTL state snapshots on gate-level simulation by using the matching points from the formal verification tool.
Strober is available as a plug-in of MIDAS