FASED: FPGA-Accelerated Simulation and Evaluation of DRAM
Authors: David Biancolin, Sagar Karandikar, Donggyu Kim, Jack Koenig, Andrew Waterman, Jonathan Bachrach, and Krste AsanovicDate: February 2019
Conference: International Symposium on Field-Programmable Gate Arrays (FPGA 2019), Seaside, CA
This work presents the generator of high-fidelity, runtime-reconfigurable, last-level cache and DRAM timing models provided by MIDAS and used in FireSim.