Ameer Haj Ali

Ameer is a first-year Ph.D. student in the ADEPT Lab and RISE Lab at UC Berkeley. His current research is focused on Hardware/Software Codesign, Auto-Tuning, Machine Learning, Reinforcement Learning, ASIC Design, High Performance Computing, and hardware for machine learning.

Ameer finished his M.Sc. studies at the Technion – Israel Institute of Technology in 2018, where he worked on using emerging memory technologies to enhance the performance of modern computer systems with Professor Shahar Kvatinsky and made multiple journal and conference publications. He received the B.Sc. degree in computer engineering, summa cum laude (the valedictorian), in 2017 from the Technion - Israel Institute of Technology. From 2015 to 2016 he was with Mellanox Technologies as a chip designer where he worked on creating design and automation tools that facilitated the formal and dynamic verification process.

Alon Amid

Alon is a Ph.D. student in the ADEPT Lab at UC Berkeley (formerly ASPIRE). His research interests include parallel, distributed, and energy efficeint computing properties - in both edge and warehouse-scale computers. He is also interested in the way new computing micro-architectures interact with full-system software.

Alon received his B.Sc. in Electrical Engineering in 2016 from Technion - Israel Institute of Technology.

David Biancolin

David is a student in the ADEPT Lab interested everything related to VLSI design, from transistors to CAD to computer architecture. As part of the FireSim project, his research focusses on developing techniques that make FPGAs more powerful hosts of full-system simulators. Specifically, he works on the FIRRTL compiler at the heart of FireSim, called MIDAS, which automatically generates bit-exact, host-decoupled simulators from SoC RTL.

David graduated from the University of Toronto in 2014, with a BASc. in Engineering Science (ECE option). His undergraduate thesis was supervised by Professor Jonathan Rose.

Hasan Nazim Genc

Hasan is a PhD candidate advised by Krste Asanović. Currently, he is working on the Gemmini project. Gemmini is a platform for full-system, full-stack evaluation of DNN accelerator workloads. In the past, he's also contributed to the Chisel hardware construction language.

Hasan recieved his B.S. in Electrical and Computer Engineering from the University of Texas at Austin, where he investigated the compute requirements of autonomous drones.

Abraham Gonzalez

Abraham is a first-year Ph.D student in the ADEPT Lab at UC Berkeley. His research interests are in warehouse-scale computing and high performance microarchitectures. He currently works on the BOOM project and the FireSim project for research.

Abraham received a B.S. in Electrical and Computer Engineering from the University of Texas at Austin in 2018. During his undergraduate education, he worked on research ranging from QCA arithmatic circuits to semiconductor manufacturing variation to adding SMT support in ZSIM.

Adam Izraelevitz

Adam is a 6th year Ph.D. student in the ASPIRE Lab at Cal. His research interests are hardware design methodologies, programming languages, and design space exploration of hardware designs.

Along with Patrick Li and Jonathan Bachrach, he designed and implemented FIRRTL, the new intermediate representation of Chisel.

Adam received his B.S. in Electrical & Computer Engineering from Cornell University in 2013.

Sagar Karandikar

Sagar is a Ph.D. student in the ADEPT and RISE Labs at UC Berkeley, advised by Krste Asanovic.

His research focuses on exploring hardware-software co-design in warehouse-scale machines, covering the whole computing stack from applications to microarchitecture. He leads the FireSim project, which enables cycle-accurate simulation of thousand-node clusters interconnected by high-performance networks using FPGAs in the cloud (see the ISCA '18 paper for more). FireSim was selected as one of IEEE Micro's "Top Picks from Computer Architecture Conferences" for 2018. He also contributes to the MIDAS project. Other projects he works on are listed on his website, sagark.org.

Sagar received a M.S. in Computer Science from UC Berkeley in 2018 and a B.S. in Electrical Engineering and Computer Sciences from UC Berkeley in 2015. In summer 2015, he was the lecturer for CS61C at Berkeley.

Donggyu Kim

Donggyu is a sixth-year Ph.D. student in the ASPIRE Lab at UC Berkeley. He is interested in computer system simulation and verification.

Donggyu received his B.S. in Computer Science and Mathematics from Pohang University of Science and Technology(POSTECH), Korea, in 2013.

Dayeol Lee

Dayeol is a Ph.D. student in the ADEPT Lab and RISE Lab at UC Berkeley. He is interested in hardware/system-level security as well as warehouse-scale computer systems.

Dayeol received his B.S. and M.S. in Computer Science and Engineering from Pohang University of Science and Technology (POSTECH).

Albert Magyar

Albert is a fifth-year Ph.D. student in the ASPIRE Lab.

Albert received his B.A. in Computer Science and B.S. in Nuclear Engineering from UC Berkeley in 2013.

Howard Mao

Howard is a Ph.D. Student in the ADEPT Lab working on hardware architectures for warehouse scale computers. He is a major contributor to the FireSim project.

Howard received his B.S. in Computer Engineering from Columbia University School of Engineering and Applied Science in 2014 and an M.S. in Electrical Engineering from UC Berkeley in 2016.

Albert Ou

Albert is a fourth-year Ph.D. student in the ADEPT Lab at UC Berkeley. His research interests are in data-parallel architectures and VLSI design for energy efficiency.

Albert received his M.S. in Computer Science in 2015 and B.S. in Electrical Engineering and Computer Sciences in 2014, both from UC Berkeley.

Nathan Pemberton

Nathan is a PhD student studying computer architecture and operating systems for warehouse-scale computers (WSCs). He's especially interested in the concept of resource disaggregation, where the individual components of traditional servers (CPU sockets, memory, storage, etc.) are all directly accessible over the network (this is part of the FireBox Project). His work focuses on developing WSC-native programming models and the hardware needed to support those models. Evaluating this research vision requires advances in programming models and simulation infrastructure, and so he also works on the FireSim datacenter-scale, cycle-exact, simulator. His work on FireSim mostly focuses on tools and methodologies for HW/SW co-design. In particular, he works on simplifying and automating the process of building, managing, and evaluating workloads across both functional and cycle-exact simulation.

Nathan received his B.S. in Computer Engineering in 2012 from UC Santa Cruz, and his M.S. in Computer Science in 2017 from UC Berkeley. He worked on an appliance for analytic database processing at Oracle Labs for 2 years before coming to Berkeley.

Colin Schmidt

Colin is a 6th year Ph.D. student in the ASPIRE Lab at Cal. He is generally interested in hardware-software co-design to improve energy-efficiency. This frequently includes hardware specialization, data-parallel acclerators, and tools and compilers to support them.

Colin received his B.S. in Electrical & Computer Engineering with a double major in Computer Science from Cornell University in 2013.

Lisa Wu

Lisa is a postdoctoral research fellow in the ADEPT Lab at UC Berkeley. Her research interests include comptuer architecture and microarchitecture, hardware-software co-designs, accelerators, energy-efficient computing, and emerging applications related to healthcare such as genomics analytics for precision medicine and big data such as database and graph analytics.

Lisa has a PhD in computer science from Columbia University, a MS in computer science and engineering from University of Michigan Ann Arbor, and a BS in electrical and computer engineering from University of Illinois Urbana-Champaign. Prior to pursuing her doctorate, she was a computer and performance architect at Intel for many years, architecting various Xeon and IPF server processors including leading the Xeon Phi Vector Processing Unit architecture.